1. Field of the Invention
The present invention relates to a semiconductor device used for efficiently changing the position of display data displayed on a display device, an image display system using the semiconductor device, and an electronic system using the image display system. More particularly, the present invention relates to the sequence of supplying display data, which is stored in a display RAM (Random Access Memory), to an image display system.
2. Related Art
For displaying data on a liquid crystal display (hereinafter referred to as an xe2x80x9cLCDxe2x80x9d) which serves as a display device, a semiconductor device called an LCD driver is employed. There are two types of LCD drivers, i.e., a segment driver (hereinafter referred to as an xe2x80x9cX driverxe2x80x9d) for driving data electrodes of the LCD, and a common driver (hereinafter referred to as a xe2x80x9cY driverxe2x80x9d) for driving scanning electrodes of the LCD. The X driver is a circuit for receiving display data to be displayed on the LCD from a display RAM through a circuit called a display controller, and converting the received data into a voltage required for driving the LCD. The Y driver is a circuit for receiving, through the display controller, data to select a line in which a data signal supplied from the X driver is to be written, and converting a voltage for selection/non-selection into the voltage required for driving the LCD. Usually, the selected line is scanned by a line-at-a-time scheme.
With advances in the semiconductor manufacturing technology and the circuit technology, it has recently become possible to integrate an X driver, a display RAM and a display controller into one IC, or further integrate a Y driver and a display power supply circuit for an LCD as well. As a result, a reduction in the number of chips used in a display system and a reduction in power consumed by the display system are promoted.
FIG. 2 is a schematic block diagram of a conventional image display system.
The conventional image display system includes a microprocessor (hereinafter referred to as an xe2x80x9cMPUxe2x80x9d) 1. The MPU 1 is constituted by a central processing unit, and has the function of generating a signal to write display data, which is to be displayed on an LCD, in a display RAM. An oscillator 2 has the function of generating a reference clock required for displaying data on the LCD. A RAM built-in X driver 3 is a one-chip unit incorporating a display RAM 31, a display controller which is, though not denoted in FIG. 2, made up of an MPU logic 33 and a display logic 34, and an X driver 32. A Y driver 4 is a circuit for receiving, through the display controller, data to select a line in which a data signal supplied from the X driver 32 is to be written, and converting a voltage for selection/non-selection into a voltage required for driving the LCD. A display power supply 5 has the function of generating a voltage required for displaying data on the LCD. LCD panels 61, 62 are each the same panel, but represent the cases displaying different screen images. The display RAM 31 is constituted by a dual port RAM that interfaces with the MPU and the display system in asynchronous relation. The X driver 32 is a circuit for converting the display data read out of the display RAM 31 into a voltage required for displaying data on the LCD. The MPU logic circuit 33 has the function of performing processing related to the MPU 1 such as processing of commands sent from the MPU 1 and control of the display data to be read out of and written in the display RAM 31. The display logic circuit 34 has the function of performing control related to display such as control of the operation of reading the display data out of the display RAM 31 and supplying the read-out data to the X driver 32 and control of the Y driver 4. A memory area 301 serves as an area for storing the display data. An MPU read/write circuit 302 is a circuit for performing control of reading/writing made on the memory area 301. An MPU row address 303 is a decoder for indicating an address of the memory area 301 in the Y (row) direction in the reading/writing mode of the MPU. An MPU column address 304 is a decoder for outputting an address of the memory area 301 in the X (column) direction in the reading/writing mode of the MPU. A display address 305 is a decoder for reading the display data, which is to be supplied to the X driver 32, from among the display data stored in the memory area 301.
The LCD panel 61 has a display capacity of 320xc3x97240 dots; namely, it has 240 lines of common electrodes on the left side of the panel and 320 lines of segment electrodes on the upper side thereof. The display RAM 31 incorporated in the RAM built-in X driver 3 has the same display capacity as the LCD panel 61, i.e., 320xc3x97240 bits. The MPU column address 304 of the display RAM 31 includes 320 addresses corresponding to the number of dots in the X direction of the LCD panel 61. Because of 8-bit simultaneous writing, the MPU row address 303 of the display RAM 31 includes 30 addresses corresponding to a result of dividing 240, i.e., the number of dots in the Y direction of the LCD panel 61, by 8. The MPU 1 can write data, which is to be displayed, at any desired position in the display RAM 31 through the MPU logic circuit 33 and the MPU read/write circuit 302 by designating any desired addresses to the MPU column address 304 and the MPU row address 363 through the MPU logic circuit 33. One bit of the display data corresponds to one dot for display in the LCD panel 61. If the display data is xe2x80x9c0xe2x80x9d, the predetermined dot in the LCD panel 61 corresponding to that display data is displayed white, and if the display data is xe2x80x9c1xe2x80x9d, it is displayed black.
The display address 305 includes 240 addresses corresponding to the number of dots in the Y direction of the LCD panel 61. The display logic circuit 34 designates any one of the display addresses xe2x80x9c0xe2x80x9d-xe2x80x9c239xe2x80x9d. When the display address is designated, the display RAM 31 outputs data of 320 bits corresponding to the number of dots in the X direction of the LCD panel 61, and supplies the data to the X driver 32. The X driver 32 converts the received display data into a voltage required for driving the LCD panel 61, and supplies the voltage to the LCD panel 61 for driving the same.
FIG. 3 is a time chart of signals at respective points for explaining the operation of the image display system of FIG. 2. In FIG. 3, the vertical axis represents a logical level and the horizontal axis represents time. The operation of FIG. 2 will be described below with reference to FIG. 3.
A signal 401 is a reset (RES) signal. A signal 402 is a reference clock DCLK supplied from the oscillator 2. Signals 403, 412 are each an output of a not-shown address counter included in the display logic circuit 34. Signals 404, 413 are each X driver data given by the data in the display RAM 31 that is taken in by the X driver 32 at a fall of the reference clock DCLK. A signal 405 is a selection signal YDATA supplied to the Y driver 4. Signals 406-411 are selected data transferred by a 240-step shift register (not shown) in the Y driver 4.
As indicated by the signal 403, the output of the not-shown address counter included in the display logic circuit 34 is initialized to xe2x80x9c0xe2x80x9d with the rise edge of the reset signal RES. After that, the output of the not-shown address counter is counted up with the rise edge of the reference clock DCLK 402, and is returned to xe2x80x9c0xe2x80x9d upon the count reaching xe2x80x9c239xe2x80x9d as indicated by the signal 403. The signal 403, which is an output signal of the address counter, is supplied to the display address 305, whereby the display address is designated from xe2x80x9c0xe2x80x9d to xe2x80x9c239xe2x80x9d in sequence.
The YDATA 405 is a selection-signal supplied to the Y driver 4. xe2x80x9cHxe2x80x9d of the YDATA 405 corresponds to line selection and xe2x80x9cLxe2x80x9d corresponds to non-selection. The YDATA 405 turns to xe2x80x9cHxe2x80x9d from the rise edge of the reset signal RES to the rise edge of the next reference clock DCLK. After that, the YDATA 405 turns to xe2x80x9cHxe2x80x9d each time 240 pulses of the reference clock DCLK are outputted. The Y driver 4 takes in the YDATA with the fall edge of the reference clock DCLK and transfers the YDATA by the 240-step shift register. (not shown) in the Y driver 4. Outputs of respective registers of the 240-step shift register are issued as the signals 406-411 and provide data supplied to 240 terminals of the Y driver 4. The outputs of the respective registers are each converted into a voltage required for displaying data on liquid crystals, and are then supplied to the LCD panel 61 for driving the LCD panel 61. The data of the signal Y0 (406) is supplied to an uppermost terminal of the LCD panel 61 after being converted into a voltage required for displaying data on liquid crystals, and the data of the signal Y1 (407) is supplied to another terminal positioned adjacently under the uppermost terminal. Likewise, the data of the signal Y2 (408) is supplied to still another terminal positioned adjacently under the second uppermost terminal. In other words, one of the 240 lines of common electrodes is selected each time, and the selected electrode is scanned downward from the uppermost electrode.
The display address 305 of the display RAM 31 includes addresses assigned with xe2x80x9c0xe2x80x9d-xe2x80x9c239xe2x80x9d from an upper end to a lower end. As shown in FIG. 2, data xe2x80x9cxe2x96xa1xe2x80x9d, xe2x80x9c∘xe2x80x9d and xe2x80x9cxcex94xe2x80x9d are written by the MPU 1 in the memory area 301 throughout the display addresses xe2x80x9c0xe2x80x9d-xe2x80x9c239xe2x80x9d. Those display data are each symbolically indicated, taking into account that a dot in the memory area 301 where xe2x80x9c1xe2x80x9d has been written is displayed black and a dot therein where xe2x80x9c0xe2x80x9d has been written is displayed white. In fact, the display data is electrically written in the memory area 301.
When the display address is initialized to xe2x80x9c0xe2x80x9d by the reset signal RES as indicated by the address counter output signal 403 in FIG. 3, the X driver 32 outputs the display data at the display address xe2x80x9c0xe2x80x9d to the segment electrodes with the fall edge of the next reference clock DCLK as indicated by the X driver data 404. At this time, the Y driver 4 is outputting the selection signal to the uppermost common electrode of the LCD panel 61 as indicated by the signal Y0 (406). Therefore, the data at the display address xe2x80x9c0xe2x80x9d is written and displayed in the uppermost line of the LCD panel 61. With the fall edge of the further next reference clock DCLK, the X driver 32 outputs the display data at the display address xe2x80x9c1xe2x80x9d to the segment electrodes as indicated by the X driver data 404. At this time, the Y driver 4 is outputting the selection signal to the second uppermost common electrode of the LCD panel 61 as indicated by the signal Y1 (407). Therefore, the data at the display address xe2x80x9c1xe2x80x9d is written and displayed in the second uppermost line of the LCD panel 61. Likewise, with the fall edge of the further next reference clock DCLK (402), the further next display data is written and displayed in the further next selected line. Thus, the data xe2x80x9cxe2x96xa1xe2x80x9d, xe2x80x9c∘xe2x80x9d and xe2x80x9cxcex94xe2x80x9d are written in the display RAM 31 at xe2x80x9c0xe2x80x9d-xe2x80x9c239xe2x80x9d of the display address, the display address is advanced while being counted up from xe2x80x9c0xe2x80x9d to xe2x80x9c239xe2x80x9d, and the common electrodes are selected one by one from the uppermost side by a line-at-a-time scheme. Consequently, as shown in FIG. 2, the display data is now displayed on the LCD panel 61 from the upper side to the lower side in accordance with the order of the display addresses xe2x80x9c0xe2x80x9d-xe2x80x9c239xe2x80x9d of the display RAM 31.
Then, when the display address is initialized to, e.g., xe2x80x9c120xe2x80x9d by the reset signal RES (401) as indicated by the address counter output signal 412 in FIG. 3, the X driver 32 outputs the display data at the display address xe2x80x9c120xe2x80x9d to the segment electrodes with the fall edge of the next reference clock DCLK (402) as indicated by the X driver data (413). At this time, the Y driver 4 is outputting the selection signal to the uppermost common electrode of the LCD panel 62 as indicated by the signal Y0 (406). Therefore, the data at the display address xe2x80x9c120xe2x80x9d is written and displayed in the uppermost line of the LCD panel 62. With the fall edge of the further next reference clock DCLK (402), the X driver 32 outputs the display data at the display address xe2x80x9c121xe2x80x9d to the segment electrodes as indicated by the X driver data (413). At this time, the Y driver 4 is outputting the selection signal to the second uppermost common electrode of the LCD panel 62 as indicated by the signal Y1 (407). Therefore, the data at the display address xe2x80x9c121xe2x80x9d is written and displayed in the second uppermost line of the LCD panel 62. Likewise, with the fall edge of the further next reference clock DCLK (402), the further next display data is written and displayed in the further next selected line. Assume now that the data xe2x80x9cxe2x96xa1xe2x80x9d, xe2x80x9c∘xe2x80x9d and xe2x80x9cxcex94xe2x80x9d are written in the display RAM 31 at xe2x80x9c0xe2x80x9d-xe2x80x9c239xe2x80x9d of the display address. On the other hand, the display address is counted up from xe2x80x9c120xe2x80x9d to xe2x80x9c239xe2x80x9d, returned to xe2x80x9c0xe2x80x9d upon reaching xe2x80x9c239xe2x80x9d, and counted up again from xe2x80x9c0xe2x80x9d to increase one by one, and the common electrodes are selected one by one from the uppermost side by a line-at-a-time scheme. Consequently, as shown in FIG. 2, the data in the lower side (i.e., the display addresses xe2x80x9c120xe2x80x9d-xe2x80x9c239xe2x80x9d) are now displayed in the upper side (1-120 lines from the uppermost) of the LCD panel 62, and the data in the upper side (i.e., the display addresses xe2x80x9c0xe2x80x9d-xe2x80x9c119xe2x80x9d) are now displayed in the lower side (121-240 lines from the uppermost) of the LCD panel 62.
The display address of the address counter (not shown) included in the display logic circuit 34 is set to a predetermined initial value at the timing of the reset signal RES (401). The MPU 1 can freely set the initial value of the display address through the MPU logic circuit 33. Accordingly, the MPU 1 can scroll a screen vertically just by writing, in the address counter not shown in FIG. 3, the initial value of the display address which is to be displayed at the uppermost end of the LCD panel 61, without rewriting the display data in the display RAM 31.
With the above construction wherein the address counter returns to xe2x80x9c0xe2x80x9d after counting up to xe2x80x9c239xe2x80x9d, however, a full screen of the LCD panel 61 is scrolled. In case, for example, that an image which is not to be scrolled is displayed in the upper or lower side of an active area of the LCD panel 61 and a part of the screen is to be scrolled, the display data in an area of the display RAM 31, which is to be scrolled, must be rewritten from the MPU 1 through the MPU logic circuit 33. In such a case, the number of accesses from the MPU 1 to the RAM built-in X driver 3 is much increased and power consumption of the display system is increased correspondingly. Further, the following problem has been experienced. For example, if another interrupt signal is applied to the MPU 1 during rewriting of the display data to be scrolled and the rewriting of the display data is suspended halfway, the display data under the rewriting in the course of scrolling appears on the LCD panel 61.
In view of the problems described above, an object of the present invention is to provide a semiconductor device, an image display system, and an electronic system employing them, which have succeeded in overcoming the above-described problems.
To achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor device comprising a memory for storing display data, and a voltage converting unit for converting a logical voltage based on the display data into a driving voltage for driving a display device, the display data being read out of the memory in accordance with a reference clock, the driving voltage being converted corresponding to the read-out display data and being supplied to the display device, wherein the semiconductor device further comprises a counting unit for counting an address of the memory and registers for storing any desired addresses, and the sequence of reading the display data stored in the memory is optionally set in accordance with the contents of the registers.
According to a second aspect of the present invention, there is provided a semiconductor device comprising a memory for storing display data, a display controller for reading the display data out of the memory in accordance with a reference clock and supplying the read-out display data to a voltage converting unit, and the voltage converting unit for converting a logical voltage based on the supplied display data into a driving voltage for driving a display device and supplying the driving voltage to the display device, wherein the display controller comprises a counting unit for counting an address of the memory and registers for storing any desired addresses, and the sequence of reading the display data stored in the memory is optionally set in accordance with the contents of the registers.
According to a third aspect of the present invention, the image display system includes at least one fixed display area and at least one display area capable of being scrolled.
With the construction set forth above, since the present invention includes the registers for storing any desired addresses, the sequence of designating the display address of the memory for storing the display data, which is supplied to the display device, is set such that after counting up from one desired address to another desired address, counting is skipped to still another desired address and then continued to further another desired address. A displayed image is therefore partly scrolled without rewriting the data in the memory. As a result, the semiconductor device of the present invention is suitably employed in an image display system and an electronic system.